A Low-Memory Address Translation Mechanism for Flash-Memory Storage Systems

While flash-memory has been widely adopted for various embedded systems, the performance of address translation has become a critical issue for the design of flash translation layers. The aim of this paper is to improve the performance of existing designs by proposing a caching mechanism for efficient address translation. A replacement strategy with low-time complexity and low-memory requirements is proposed to cache the most recently used logical addresses. According to the experiments, the proposed method has shown its efficiency in the reducing of the address translation time.